ds298 april 24, 2009 www.xilinx.com 1 product specification ? 2008-2009 xilinx, inc., xilinx, the xilinx logo, virtex, spartan, ise and other designated brands included herein are tradema rks of xilinx in the united states and other countries. powerpc is a trademark of ibm corp. and used under license. all other trademarks are the property of their res pective owners. introduction the jtagppc controller is a wrapper for the jtagppc and jtagppc440 fpga primitives. the jtagppc and jtagppc440 primitives allow the powerpc? 405 pro- cessor and the powerpc 440 processor, respectively, to connect to the jtag chain of the fpga. for more infor- mation about connecting the ppc405 processor to the fpga jtag chain, refer to the jtag debug port section of the powerpc 405 processor block reference guide . for more information about connecting the powerpc 440 processor to the fpga jtag chain, refer to the jtag interface section of ug200 , embedded processor block in virtex?-5 fpgas reference guide . features ? wrapper for the jtagppc and jtagpc440 primitives ? enables the debug port of the powerpc to be connected to the fpga jtag chain ? can connect up to two powerpc primitives ? automatically instantiat es and connects second unused powerpc processor in any dual-powerpc device jtagppc controller (v2.01c) ds298 april 24, 2009 product specification logicore? facts core specifics supported device family see edk supported device families . version of core jtagppc_cntlr v2.01c resources used min max slices n/a n/a luts 0 1 ffs 0 0 block rams 0 0 special features in virtex-4: jtagppc in virtex-5: jtagppc440 provided with core documentation product specification design file formats vhdl constraints file n/a verification n/a instantiation template n/a reference designs none design tool requirements xilinx implementation tools see to o l s for requirements. verification simulation synthesis support provided by xilinx, inc.
jtagppc controller (v2.01c) 2 www.xilinx.com ds298 april 24, 2009 product specification functional description the jtagppc controller shown in figure 1 is a wrapper for the jtagppc and jtagppc440 fpga primitives. in fpga devices containing two powerpc processor blocks (as listed in table 2 ), if the jtagppc con- troller is used to connect any powerpc to the fpga jt ag chain, then the design netlist must instantiate both powerpc processors and connect both of them to the jtagppc controller, even if the second powerpc processor instance is unused in the appl ication. beginning with version 2.01, the jtagppc controller wrapper automatically instantiates and connects the second unused powerpc processor if it is not already instantiated in the design. jtagppc controller i/o signals the i/o signals for the jtagppc controller are listed and described in table 1 . all signals listed in table 1 are compatible with both the powerpc 405 and powerpc 440 processors. x-ref target - figure 1 figure 1: jtagppc controller block diagram table 1: jtagppc controller i/o signals signal name interface i/o initial state description trstneg 1 system i jtag reset signal from user/external logic for all powerpc processors haltneg0 1 system i processor halt si gnal to first powerpc dbgc405debughalt0 1 ppc_0 o haltneg0 halt signal to first powerpc c405jtgtdo0 (1) ppc_0 i jtag tdo signal from first powerpc c405jtgtdoen0 1 ppc_0 i jtag tdoen signal from first powerpc jtgc405trstneg0 1 ppc_0 o trstneg jtag reset signal to first powerpc jtgc405tck0 1 ppc_0 o same as primitive jtag tck signal to first powerpc jtagppc primitive d s 29 8 _01_031709 tdo c405jtgtdo0 controlled b y c_device: s elect s ppc_0 in s ingle ppc device s ; ppc_1, otherwi s e c405jtgtdo1 c405jtgdoen0 dbgc405debughalt0 jtc405tr s neg0 jtc405tr s neg1 dbgc405debughalt1 jtgc405di1 jtgc405*0 jtgc405*1 c405jtgdoen1 c405jtg*0 halneg0 halneg1 tr s tneg
ds298 april 24, 2009 www.xilinx.com 3 product specification jtagppc controller (v2.01c) jtagppc controller parameters the parameters for the jtagppc controller are listed in table 2 . allowable parameter combinations there are no restrictions on parameter combinations. parameter - port dependencies when c_device indicates a single powerpc device (as listed in table 2 ), ports dbgc405debughalt1, c405jtgtdo1, c405jtgtdoen1, jtgc405trstneg1, jtgc405tck1, jtgc405tdi1 and jtgc405tms1 must remain unconnected. when c_device indicates a dual powerpc device (as listed in table 2 ), ports dbgc405debughalt1, c405jtgtdo1, c405jtgtdoen1, jtgc405trstneg1, jtgc405tck1, jtgc405tdi1 and jtgc405tms1 must be connected to the second powerpc instance only if it is instantiated in the design. jtgc405tdi0 1 ppc_0 o same as primitive jtag tdi signal to first powerpc jtgc405tms0 1 ppc_0 o same as primitive jtag tms signal to first powerpc haltneg1 2 system i processor halt signal from user/external logic (ex: vision probe) dbgc405debughalt1 2 ppc_1 o haltneg1 halt signal to second powerpc c405jtgtdo1 (2) ppc_1 i jtag tdo signal from second powerpc c405jtgtdoen1 (2) ppc_1 i jtag tdoen signal from second powerpc jtgc405trstneg1 (2) ppc_1 o trstneg jtag reset signal to second powerpc jtgc405tck1 (2) ppc_1 o same as primitive jtag tck signal to second powerpc jtgc405tdi1 (2) ppc_1 o same as primitive jtag tdi signal to second powerpc jtgc405tms1 (2) ppc_1 o same as primitive jtag tms signal to second powerpc 1. must be connected if core is used. 2. should be left unconnected in designs that do not contain a second powerpc instance. table 2: jtagppc controller parameters parameter name description allowed values tool calculated type c_device target device identifier. used to determine how many powerpc primitives exist in the part. single powerpc devices: 4vfx12, 4vfx20, 5vfx 3 0t, 5vfx70t. dual powerpc devices: 4vfx40, 4vfx60, 4vfx100, 4vfx140, 5vfx100t, 5vfx115t, 5vfx1 3 0t, 5vfx180t. yes string table 1: jtagppc controller i/o signals (cont?d) signal name interface i/o initial state description
jtagppc controller (v2.01c) 4 www.xilinx.com ds298 april 24, 2009 product specification jtagppc controller register descriptions not applicable. jtagppc controller interrupt descriptions not applicable. support xilinx provides technical support for this logicore product when used as described in the product documentation. xilinx cannot guaran tee timing, functionality, or supp ort of product if implemented in devices that are not defined in the documentation, if customized beyond that allowed in the product documentation, or if changes are made to any section of the design labeled do not modify . reference documents ? powerpc 405 processor block reference guide ? ug200 , embedded processor block in virtex-5 fpgas reference guide revision history the following table shows the revision history for this document. notice of disclaimer xilinx is providing this product documentation, hereinafte r ?information,? to you ?as is? with no warranty of any kind, express or implied. xilinx make s no representation that the informat ion, or any particular implementation thereof, is free from any claims of infringement. you ar e responsible for obtaining any rights you may require for any implementation based on the info rmation. all specifications are subj ect to change without notice. xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the information or any implementation based thereon, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. except as stated herein, none of the information may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanic al, photocopying, recording, or otherwi se, without the prior written consent of xilinx. date version revision 8/12/2008 1.0 initial release. 4/24/2009 2.0 removed support for virtex-ii devices. replaced references to supported device families and tool names with hyperlink to pdf file.
|
